Microchip

Description

This pin is only available on the AT17LV512A /010A/002A. RESET/OE. RESET ( Active Low) / Output Enable (Active High) when SER_EN is High. A Low logic AT17LV65(1), AT17LV128(1), AT17LV256,. AT17LV512 , AT17LV010, AT17LV002, AT17LV040. FPGA Configuration EEPROM Memory. 3.3V and 5.0V System The internal oscillator of the AT17LV512A /010A/020A/002A. EEPROM is enabled by default, but is disabled for the AT17LV512 /010/020/002/040. EEPROMs Procedure Select /M: Enable AT17LV512A /010A/020A/002A/040 Internal. Clock . 2. Options Default or previous settings are given. You may need to modify. AT17LV512A -10JU-T. January 1, 2017. AT24701-0T4X. C0004. AT24701-0T4X. January 1, 2017. AT24C01C-PUM. SL901. AT24C01C-PUM. January 1, 2017.